Boolean Chaotic Circuits

The logic circuit we implement with the electronic gates is represented in figure 1 below, where nodes 1 and 2 perform the XOR operation of their inputs and node 3 performs the XNOR (the operation NOT applied on the XOR).

[Diagram showing network topology]
Fig. 1: Logic network of Boolean chaotic circuit.

As we can see from the figure, there are three nodes and six time delays. The Boolean delay equations to describe this network is

(1) x1(t)  =  x2(t12) ⊕ x3(t-τ13),
(2) x2(t)  =  x1(t21) ⊕ x2(t-τ22),
(3) x3(t)  =  x1(t31) ⊕ x3(t-τ33) ⊕ 1,

Differently from the single XOR with two delays, the state with all the variables remaining constant at 0 is not a solution, neither any constant state. Thus, the system will oscillate, at least periodically, whenever the gates are able to perform the correct logic. This is important, because the electronic circuit is self-starting and contains no steady-state.

To implement this logic circuit in practice, we chose a family of digital logic gates fabricated by Texas Instruments (SN74AUC) for which the low logic state 0 corresponds to 0 V an the high logic state 1 corresponds to a positive voltage, nominally, the supply voltage VCC used to power the devices. Most of the gates from this logic family operate in the following manner: If an input voltage is below VCC/2 this input is considered low (0), if an input voltage is above VCC/2 this input is considered high (1). The logic device outputs a current adequate to make the output voltage match the prescribed logic function of the inputs, but there are limitations on the maximum amount of current and response speed. The nominal range of supply voltages is 0.8 V to 3.3 V. Higher supply voltages could damage the devices. Some of the devices have Schmitt-trigger inputs, that is, the threshold used to determine whether the input state is high or low depends on the output state. If the output is on the high state and one of the inputs is on the high (low) state satisfying the correct logic function, the threshold for this input to be considered low (high) is 0.3 VCC (0.7 VCC).

The rise/fall times of the gates depend on the supply voltage and can be as fast as 0.14 ns. The higher the supply the faster the output voltage can change. The gates also take a time to make a transition in the inputs manifest its effect at the output. This time is called propagation delay, and also decreases with the supply voltage. The propagation delay can be in the range of 0.45 ns to 600 ns. We use accumulated propagation delay of a few gates mounted in series to generate the delays times τij. Thus, changing the value VCC changes the values of the delays in the circuit. The delays are also due to propagation in the circuit tracks, and we can use coaxial cables to make the distance traveled by the signals longer. The actual circuit diagram is shown in figure 2 below and a photo of the board in figure 3.

Fig.2: Schematic diagram of the circuit.

 

Fig.3: A chaotic Boolean circuit.

 

We chose single-gate devices to avoid undesired crosstalk between the elements. Follow these links to see the manufacturer's webpage and data sheets on the gates we used:
Single gate XOR - SN74AUC1G86
Single gate inverter - SN74AUC1G04
Single gate Schmitt-trigger inverter - SN74AUC1G14
Single gate Schmitt-trigger buffer - SN74AUC1G17

We usually order the printed circuit boards (PCB) via the internet from ExpressPCB, Pad2pad or PCB123. The layout of the board can be prepared with software offerred by the company, but they also may accept gerber files. Click here to download a file with one example of a 4-layer board layout prepared with the software from ExpressPCB. Some companies may also solder the electronic components, but we solder ours ourselves. Tips for soldering Surface Mount Technology (SMT) devices by hand may be found on the internet (here is one site, here is another).

To measure the state of the logic variables we need a fast oscilloscope or acquisition device. The bandwidth should be on the order of 0.35/trise, and the sampling rate at least twice as fast as the inverse of the minimum pulse width, which is on the order of the propagation delay. A buffer gate can be used to drive the signal through a cable connecting the measurement equipment. If the input impedance of the measurement device is 50 Ω a voltage drop is to be expected. High impedance should be avoided at the end of long cables (tens of centimeters) because of reflections that can distort the true waveform. High impedance probes can be used if the high impedance part is physically close to the point under test. We developed a home-made high-impedance probe by soldering a 600 Ω SMT resistor to the end of a coaxial cable. The ground mail of the cable can be tapered to form a ground connector that also must be close to the point under test and properly grounded. If we use this high impedance probe, the voltage measured by the 50 Ω oscilloscope is much smaller than the actual voltage in the circuit (roughly by a factor of 0.077 = 50/650) but the factor is constant and the attenuation flat as function of frequency up to more than 2 GHz. Commercial high-impedance active probes are also a good choice.

Fig.4: Another chaotic Boolean circuit, with SMA connectors (Amphenol RF 901-144-8RFX) for input and output.

 

Close to the supply lead of every gate we put a SMT ceramic capacitor (10 nF to 100 nF, see this data sheet for one example GRM155F50J104ZA01D) to prevent oscillations in the supply voltage. It is also a good practice to have a large electrolytic capacitor for the whole board (150 µF, ex: UPS1C151MED).


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